1. Technical Field
The present invention relates generally to semiconductor packages, and more specifically to a method and apparatus for packaging large dies in such packages.
2. Background Art
The trend toward miniaturization of electronic equipment has required high-density packaging of semiconductor devices. To meet this requirement, semiconductor packages have been reduced both in area and thickness, while the size and complexity of dies within the packages have increased. As a result, there has been a growing demand for semiconductor packages which accommodate large dies.
A leadless leadframe package (LLP) is a semiconductor package design that contemplates the use of a metal (typically copper) leadframe structure in the formation of a chip scale package (CSP).
A typical leadless leadframe package includes a copper leadframe strip or panel which is patterned, typically by etching, to define a plurality of arrays of chip substrate features. Each chip substrate feature includes a die pad and a plurality of bonding fingers disposed about their associated die pad. A plurality of package electrical input-output terminal contact pads (contact pads) are defined on the bottom surface of the bonding fingers typically with an etch process. A plurality of very fine tie bars is used to mechanically connect and support the die pad and bonding fingers during manufacture.
During assembly, dies are attached to the respective die pads and conventional wire bonding is used to electrically couple bond pads on each die to their associated bonding fingers on the leadframe strip. After the wire bonding, a plastic cap is molded over the top surface of each of the array of wire bonded dies. The dies are then singulated and tested using conventional sawing or punching and testing techniques.
Certain semiconductor packages include a die pad and a plurality of bonding fingers with inner and outer contact pads thereby allowing semiconductor packages to be manufactured in a very compact size while being able to accommodate dies having a relatively large number of contacts In these semiconductor packages, however, the size of the die that can be used is limited by the size of the die pad depending upon the particular package being used. Two of these types of semiconductor packages are the QFN (Quad Flat-Packed Non-Leaded) and Leadframe Ball Grid Array (BGA) packages. These types of packages are desirable because they have a low vertical profile enabling them to be placed into small electronic products.
Attempts have been made to adapt these types of packages so that a large die can be used within a given sized package while maintaining the low profile of the package. A “large” die is a die that has a pair of opposing edges extending laterally beyond the edges of the die pad in a semiconductor package.
One such attempt includes providing a die pad with a centrally located raised “up-set” portion that raises the die pad above the upper surface of the bonding fingers so the outer periphery of the die can extend laterally beyond the edges of the die pad. This results in a support for the die pad that is substantially reduced in area thereby raising manufacturing issues during wire bonding and molding operations after the die is mounted to the die pad. The die is more likely to tilt during these operations due to the reduced support provided by the up-set portion of the die pad.
Reduced “up-set” dimensions also increase the die overhang thereby effectively reducing limiting the largest die size, because of wirebond limitation on the overhang portion of the die.
If the area of the up-set portion of the die pad is increased to reduce the amount of possible die tilt during subsequent packaging operations, less area of the die pad is available for subsequent solder joining of the die pad to a printed circuit board thereby reducing the heat removal efficiency of the package through the printed circuit board.
This type of special die pad assembly also is more expensive and difficult to manufacture.
Solutions to these problems have been long sought, but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art. Accordingly, there is a need for a semiconductor package that accommodates larger dies, but overcomes the problems mentioned above.